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Supply Chain Cost Modeling
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WIRE BOND COST MODEL

Quickly see the cost impact of design decisions

 

 

An optional enhancement is to create a model calibrated to your particular technology or to a specific supplier (internal or external). Contact us for more details.

 

Use the model to:

 

What’s the cost impact of...?

 

Flip Chip Model Parameter List

Complex Calculations, Simple Interface

 

All of our Packaging Cost Models were developed for ease of use and efficiency. Many detailed parameters are available for editing, but only a few inputs are required to run the analysis. For parameters you choose not to edit yourself, complex SavanSys algorithms automatically assign default values based on your other entries and extensive, up-to-date industry knowledge.

Design

Assembly

Fabrication

Pkg Size

Labor Rate

Labor Rate

Pkg I/O

Lot Size

Utilization

Structure

Annual Vol

Panel Size

Design Rules

Lifetime Vol

Lot Size

Stacked Vias

Wafer Probe Yield

 

Capacitors

Utilization

 

Core Material

Wafer Bump?

 

BGA Pitch

CSP Strip Size

 

umVia Count

 

 

PTH Count

 

 

Lid

 

 

Surface Finish

 

 

Die Size

 

 

Die Cost