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Supply Chain Cost Modeling
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These papers concern advanced modeling topics and project results from SavanSys users. Many of the white papers are downloadable only in .pdf format. Please contact us if you have difficulty downloading or opening any of the files.

 

 

TECHNICAL PAPERS

IC Packaging

Cost and Yield Analysis of RDL Creation in Fan-out Wafer Level Packaging (2018)

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging (2017)

A Cost Analysis of RDL-first and Mold-first Fan-out Wafer Level Packaging (2016)

Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging (2016)

Cost and Yield Analysis of Wafer-to-wafer Bonding (2015)

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste (2015)

An Analysis of Key Cost and Yield Drivers for Fan-out Wafer Level Packaging (2015)

Cost Comparison of Temporary Bond and Debond Methods For Thin Wafer Handling (2014)

Cost Comparison of Multi-Die Fan-Out Wafer Level Packaging and 2.5D Packaging With a Silicon Interposer (2013)

Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies (2013)

Cost Trade-off Analysis of PoP versus 3D TSV (2012)

Cost Comparison for Flip Chip, Wire Bond, and Wafer Level Packaging (2010)

 

PCB

Cost Comparison of Complex PCB Fabrication Using Traditional Sequential Lamination Methods Versus Interconnect with Conductive Paste (Co-authored with Ormet Circuits, Inc.)

A Technology to Reduce Pad Cratering Defects and the Impact on Product Cost (Co-authored with Integral Technology)

 

Embedded Passives

A Comparison of Small Discretes and Polymer Thick Film Embedded Resistors for Mobile Phone Applications

Activity Based Cost Modeling for Embedded Passives

Fabrication and Assembly Yield for Embedded Passives: Risks and Opportunities

Size and Cost Modeling for Embedded Passives

 

 

Miscellaneous

Optimizing Product Cost with Supply Chain Cost Modeling